hardcaml-luaversion
A lua client for interfacing hardcaml to verilator, UHDM, Verible and RTLIL front-ends
Verilator, Surelog and Verible do not generate synthesised Verilog code directly. This software bridges the gap and verifies the results using build-in minisat solver, z3 or external eqy script
Tags | Verilator Surelog UHDM Verible Yosys RTLIL |
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Author | Jonathan Kimmitt |
License | MIT |
Published | |
Homepage | https://github.com/jrrk2/hardcaml-lua |
Issue Tracker | https://github.com/jrrk2/hardcaml-lua/issues |
Maintainer | Jonathan Kimmitt |
Available | os != "win32" & arch != "riscv64" & arch != "riscv32" |
Dependencies |
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Conflicts | |
Source [http] | https://github.com/jrrk2/hardcaml-lua/releases/download/0.0.1/hardcaml-lua-0.0.1.tbz sha256=39d6b86d008d2d2408f178d0bd60ea54ea97a8e6f5d6491c9cb3314fe679cacf sha512=b20915daa25687d2c8c75c3ed57d7c353d59a1873b6f544afe8ed4253f12105a3f586f2224191c054b330458296a1605510849201af8419b11b28d673dce057c |
Edit | https://github.com/ocaml/opam-repository/tree/master/packages/hardcaml-lua/hardcaml-lua.0.0.1/opam |
No package is dependent