ppx_hardcamlversion
Rewrite OCaml records for use as Hardcaml Interfaces
An interface in Hardcaml is an OCaml record with special attributes including a bit width and RTL netlist name. Input and output ports of a hardware design can then be accessed through the OCaml record. This allows easier management of bundles of ports when working with the Simulator, Netlist generation or hierarchical designs.
Author | Jane Street Group, LLC |
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License | MIT |
Published | |
Homepage | https://github.com/janestreet/ppx_hardcaml |
Issue Tracker | https://github.com/janestreet/ppx_hardcaml/issues |
Maintainer | Jane Street developers |
Available | arch != "arm32" & arch != "x86_32" |
Dependencies | |
Source [http] | https://github.com/janestreet/ppx_hardcaml/archive/refs/tags/v0.17.0.tar.gz sha256=e4ea96d3edd794a1e3128b9c42eb97da41c95c78371caa1e9cd6842244766e1c |
Edit | https://github.com/ocaml/opam-repository/tree/master/packages/ppx_hardcaml/ppx_hardcaml.v0.17.0/opam |
Required by
- hardcaml_axi>=v0.17.0
- hardcaml_c>=v0.17.0
- hardcaml_circuits>=v0.17.0
- hardcaml_handshake>=v0.17.0
- hardcaml_of_verilog>=v0.17.0
- hardcaml_verify>=v0.17.0
- hardcaml_verilator>=v0.17.0
- hardcaml_xilinx>=v0.17.0
- hardcaml_xilinx_reports>=v0.17.0